The present invention relates to semiconductor memory circuits, and more particularly relates to memory access techniques with respect to dynamic memories.
Among the semiconductor memory circuits, dynamic random-access memories (hereinafter referred to as “DRAMs”) have been widely used as devices capable of reading and writing a large amount of data. FIG. 12 illustrates the circuit configuration of a typical DRAM which is currently in practical use. The DRAM 100 shown in FIG. 12 includes a memory cell 101, a sense amplifier 102, and a precharge circuit 103. Hereinafter, referring to a timing chart shown in FIG. 13, how the DRAM 100 reads data will be described.
First, the precharge circuit 103 is activated (PRE=“H”) when the memory cell 101 is inactive (WL=“L”), so that a pair of bit lines BL and BLX (hereinafter referred to as a “bit line pair BL and BLX”) is precharged to a voltage VDD/2 (VDD is a power supply voltage.) The precharge circuit 103 is then inactivated (PRE=“L”), while at the same time a word line WL is activated (WL=“H”), whereby a capacitor 110 in the memory cell 101 is electrically connected to the bit line BL, causing accumulated charge to be reallocated between the capacitor 110 and the bit line BL. Specifically, if the amount of charge accumulated in the capacitor 110 is larger, that is, when the memory cell 101 stores therein data “1”, the accumulated charge in the capacitor 110 is supplied to the bit line BL. On the other hand, if the amount of charge accumulated in the capacitor 110 is smaller, that is, when the memory cell 101 stores therein data “0”, the charge is transferred from the bit line BL to the capacitor 110. More specifically, suppose the case in which the data stored by the memory cell 101 is “1”. The charge reallocation results in an increase in the potential of the bit line BL by ΔV, which produces a potential difference ΔV between the bit line pair BL and BLX. The sense amplifier 102 senses and amplifies this potential difference, thereby permitting the data “1” to be read from the DRAM 100.
In recent years, the degree of integration of DRAMs has been increasing along with the advancement of minute processing techniques for semiconductor integrated circuits. In addition, in order to reduce the power consumption of such highly-integrated DRAMS, the power supply voltage has been lowered. Nevertheless, it is difficult to decrease the threshold voltage of MOS transistors in proportion to the lowering of the power supply voltage because of variations caused in fabrication processes. Therefore, in DRAMs of the above-mentioned VDD/2 precharge type, the lowered power supply voltage increases the ratio of the threshold voltage of the MOS transistors to the power supply voltage. Particularly, in DRAMs after the 0.10-μm process generation, there would be little difference between the threshold voltage of the MOS transistors forming the sense amplifier 102 and the voltage VDD/2, whose magnitude is the voltage amplitude of the bit line pair BL and BLX. In that case, activating the sense amplifier 102 would not produce a sufficient potential difference between the gate and source of those transistors, causing the sense amplifier 102 to be significantly delayed in, or become incapable of, performing sensing operation for the bit line pair BL and BLX.
In order to solve the above problem, it is preferable that the voltage between the gate and source of sense amplifier transistors be large. With respect to this, the following prior art technique has been proposed.
FIG. 14 illustrates the circuit configuration of a conventional VDD-precharge DRAM. The DRAM 200 shown in FIG. 14, which is of NMOS type, includes a memory cell 201, a sense amplifier 202, a precharge circuit 203, and a dummy cell 204. Hereinafter, data-read operation by the DRAM 200 will be discussed with reference to a timing chart shown in FIG. 15.
First, the precharge circuit 203 is activated (P=“H”) when the memory cell 201 is inactive (WL=“L”), so that a pair of bit lines BL and BLX is precharged to a voltage VDD−Vth (Vth is the threshold voltage of NMOS transistors forming the precharge circuit 203.) At this time, a signal PRE=“H”, and a dummy capacitor 220 in the dummy cell 204 is charged to a GND level. Then, the signals P and PRE are put to “L”, while at the same time a word line WL and a dummy word line DWL are activated (WL=“H”, DWL=“H”). This establishes an electrical connection between a main capacitor 210 in the memory cell 201 and the bit line BL, and between the dummy capacitor 220 in the dummy cell 204 and the bit line BLX, resulting in the reallocation of electric charge. Suppose a case in which the data stored by the memory cell 201 is “0”. The charge reallocation between the main capacitor 210 and the bit line BL reduces the potential of the bit line BL by ΔV. Likewise, the charge reallocation between the dummy capacitor 220 and the bit line BLX causes the potential of the bit line BLX to be decreased by ΔVref. In this DRAM, the dummy capacitor 220 is configured so as to have capacitance which is about half of that of the main capacitor 210, such that the decrease ΔVref in the bit line BLX potential is about half of the decrease ΔV in the bit line BL potential. The resultant potential difference caused between the bit line pair BL and BLX is sensed and amplified by the sense amplifier 202, thereby allowing the data “0” to be read from the DRAM 200 (see document 1, for example.)
Meanwhile, FIG. 16 illustrates the circuit configuration of a conventional GND-precharge DRAM. The DRAM 300 shown in FIG. 16, which is of NMOS type, includes a memory cell 301, a sense amplifier 302, a precharge circuit 303, and a reference cell (dummy cell) 304. Hereinafter, data-read operation by the DRAM 300 will be discussed with reference to a timing chart shown in FIG. 17.
First, the precharge circuit 303 is activated (EQP=“H”) when the memory cell 301 is inactive (WL0=“L”), so that a pair of bit lines BC and BT is precharged to a GND level. At this time, a signal REQP=“H”, and the dummy cell 304 is precharged to VDD/2. Then, a word line WL0 and a reference word line (a dummy word line) RFWL0 are activated (WL0=“H”, RFWL0=“H”). This establishes an electrical connection and then causes charge reallocation between a main capacitor 310 in the memory cell 301 and the bit line BC and between a dummy capacitor 320 in the dummy cell 304 and the bit line BT. Suppose a case in which the data stored by the memory cell 301 is “1”. The charge reallocation between the main capacitor 310 and the bit line BC increases the potential of the bit line BC by ΔV. Likewise, the charge reallocation between the dummy capacitor 320 and the bit line BT results in an increase of ΔVref in the potential of the bit line BT. In this DRAM, the accumulated charge in the dummy capacitor 320 is about half of the maximum amount of accumulated charge in the main capacitor 310, such that the increase ΔVref in the bit line BT potential is about half of the increase ΔV in the bit line BC potential. The resultant potential difference created between the bit line pair BC and BT is sensed and amplified by the sense amplifier 302, allowing the data “1” to be read from the DRAM 300 (see document 2, for example.)
(Document 1) Paul R. Schroeder and another person. (A 16K×1 Bit Dynamic RAM) “ISSCC Digest of Technical Papers” U.S.A. ISSCC (International Solid-State Circuits Conference) February 1997 pp. 12-13.
(Document 2) Barth and three other persons. (A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write) “ISSCC Digest of Technical Papers” U.S.A. ISSCC (International Solid-State Circuits Conference) February 2002 pp. 156-157.
In the DRAM 200 shown in FIG. 14, the bit line pair BL and BLX is precharged to the power supply voltage VDD that corresponds to the activated logic level for the word line WL and the dummy word line DWL. Therefore, even if the word line WL is activated, the main capacitor 210 cannot be electrically connected to the bit line BL, unless the voltage of the word line WL is raised to a voltage level that exceeds the voltage of the bit line BL by the threshold voltage Vth of the NMOS transistor forming the memory cell 201. This holds true for the dummy capacitor 220. Moreover, the numerous memory cells connected to the word line WL make the word line WL heavily loaded, which slows the voltage-level transition time taken in activating the word line WL. More specifically, it takes a relatively long time before the potential difference between the bit line pair BL and BLX occurs, leading to the problem that the access time for data reading is long.
In the DRAM 300 shown in FIG. 16, on the other hand, the bit line pair BC and BT is precharged to the GND-voltage level that corresponds to the inactivation logic level for the word line WL0 and the dummy word line RFWL0. Therefore, immediately after the activation level of the word line WL0 exceeds the threshold voltage Vth of the NMOS transistor forming the memory cell 301, the main capacitor 310 is electrically connected with the bit line BC. This holds true for the dummy capacitor 320. The level transition of the bit line BC occurs at a relatively high speed with respect to the level transition of the word line WL0. Therefore, the time required for data reading can be shortened, thereby enhancing the speed of memory access.
Nevertheless, the DRAM 300 shown in FIG. 16 is not designed in such a manner that different activation/inactivation voltage levels are given to the word line WL0 of the memory cell 301 and the dummy word line RFWL0 of the dummy cell 304. Normally, in DRAMs, the activation level for a word line is set at a voltage higher than the high level of output from the sense amplifier (that is, the high level of the bit line reached when the bit line is amplified by the sense amplifier.) in consideration of writing of high-level data into the memory cells. The inactivation level for the word line is preferably set at a voltage lower than the low level of the sense amplifier output (that is, the low level of the bit line reached when the bit line is amplified by the sense amplifier.) in consideration of data retention characteristics. As a result, the voltage amplitude of the word line becomes large. If a dummy word line having such large amplitude as that of the word line is also driven, the power consumption will be increased. Furthermore, if boosted power supply generated in the semiconductor chip is used in order to drive the word line of such great amplitude, the area of the power supply booster circuit will increase.
Moreover, in the DRAM 300 shown in FIG. 16, a voltage at the VDD/2 level is supplied to the dummy cell 304, which requires the DRAM 300 to include an internal power-supply-voltage generating circuit that produces the VDD/2-level voltage. Providing such a dedicated internal power-supply-voltage generating circuit, however, leads to an increase in the chip area as well as in the power consumption.
In addition, the DRAM 300 shown in FIG. 16 includes a dedicated precharge transistor 342 for supplying a VDD/2-level voltage to the dummy cell 304. The precharge transistor 342 has to be connected to the storage node of the dummy capacitor 320, to which an end of an access transistor 341 is connected. If only the storage node portion in the dummy cell 304 is formed into a different shape from that of the ordinary memory cells in the minute processing so as to be connected to the precharge transistor 342 as well, the optimization of the manufacturing process will be difficult.